The necessity increasingly arises in digital systems to generate a signal having a pulse rate which is related to a reference signal pulse rate by some (unusual) proper rational fraction, while still maintaining synchronism with the reference signal. In many instances, it is a requirement that the pulses of the generated signal be as uniformly spaced as possible within the constraint of synchronism. Sequences of such pulses are called "smooth" in contrast with uniform pulse sequences in which each pulse is separated from its predecessor by a fixed interval. The smooth pulse sequences possess a number of interesting properties in their structure. These properties are discussed in an article entitled "Smooth Pulse Sequences," by A. J. Lincoln et al. in Proceedings of the Third Annual Princeton Conference on Information Sciences and Systems, 1969, pp. 350-354.
A technique commonly employed to form synchronous pulse rate muliples uses a rate multiplier and involves detecting 0 to 1 transitions of stages of a binary counter chain. The rate multiplier technique, although often capable of forming relatively smooth sequences, does not form a true smooth sequence, as is noted in the above-cited article by A. J. Lincoln et al.
More recently, smooth pulse sequences have been generated by employing a complex digital divider arrangement including a plurality of routing circuits coupled in tandem, as disclosed in U.S. Pat. No. 4,034,302, issued to C. J. May Jr., on July 5, 1977. Although the May arrangement generates adequate smooth sequences, it is made up of a plurality of gate circuits which necessarily restrict the circuit to the generation of one fixed sequence. Additionally, this prior smooth pulse sequence generator is somewhat difficult to test and requires substantial energy as compared to modern circuit components. Thus, although this prior smooth pulse sequence generator may be adequate for some applications, it is undesirable for others.